1，Stratix IV GX

Feature

EP4SGX70 EP4SGX110 EP4SGX180 EP4SGX230 EP4SGX290 EP4SGX360 EP4SGX530

EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

 

2，Stratix IV GT

Feature

EP4S40G2 EP4S40G5 EP4S100G2 EP4S100G3 EP4S100G4 EP4S100G5

EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

 

3，Stratix IV E

Feature

EP4SE230 EP4SE360 EP4SE530 EP4SE820

EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

 

IC Stratix IV Logic/Memory FPGA

Altera? Stratix? IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. Stratix IV FPGAs are based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm process technology and surpass all other high-end FPGAs, EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517 with the highest logic density, most transceivers, and lowest power requirements. The Stratix IV device family contains three optimized variants to meet different application requirements: EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

■ Stratix IV E (Enhanced) FPGAs—up to 813,050 logic elements (LEs), 33,294 Kbits RAM, and 1,288 18 × 18 bit multipliers EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

■ Stratix IV GX transceiver FPGAs—up to 531,200 LEs, 27,376 Kbits RAM, 1,288 18 × 18-bit multipliers, and 48 full-duplex clock data recovery (CDR)-based transceivers at up to 8.5 Gbps

EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

■ Stratix IV GT—up to 531,200 LEs, 27,376 Kbits RAM, 1,288 18 × 18-bit multipliers, and 48 full-duplex CDR-based transceivers at up to 11.3 Gbps The complete Altera high-end solution includes the lowest risk, EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517 lowest total cost path to volume using HardCopy? IV ASICs for all the family variants, a comprehensive portfolio of application solutions customized for end-markets, and the industry leading Quartus? II software to increase productivity and performance. f For information about upcoming Stratix IV device features, refer to the Upcoming Stratix IV Device Features document. EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

 

Stratix IV GX Devices Stratix IV GX devices provide up to 48 full-duplex CDR-based transceiver channels per device: EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

■ Thirty-two out of the 48 transceiver channels have dedicated physical coding sublayer (PCS) and physical medium attachment (PMA) circuitry and support data rates between 600 Mbps and 8.5 GbpsEP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

■ The remaining 16 transceiver channels have dedicated PMA-only circuitry and support data rates between 600 Mbps and 6.5 Gbps 1 The actual number of transceiver channels per device varies with device selection. For more information about the exact transceiver count in each device, refer to Table 1–1 on page 1–11. 1 For more information about transceiver architecture, refer to the Stratix IV Transceiver Architecture chapterEP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

 

Stratix IV GT devices provide up to 48 CDR-based transceiver channels per device:

■ Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA circuitry and support data rates between 600 Mbps and 11.3 Gbps EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

■ The remaining 16 transceiver channels have dedicated PMA-only circuitry and support data rates between 600 Mbps and 6.5 Gbps 1 The actual number of transceiver channels per device varies with device selection. For more information about the exact transceiver count in each device, refer to Table 1–7on page 1–16. EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

1 For more information about Stratix IV GT devices and transceiver architecture, refer to the Stratix IV Transceiver Architecture chapter. Signal Integrity Stratix IV devices simplify the challenge of signal integrity through a number of chip, package, and board-level enhancements to enable efficient high-speed data transfer into and out of the device. These enhancements include: EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

■ Programmable 3-tap transmitter pre-emphasis with up to 8,192 pre-emphasis levels to compensate for pre-cursor and post-cursor inter-symbol interference (ISI)

■ Up to 900% boost capability on the first pre-emphasis post-tap

■ User-controlled and adaptive 4-stage receiver equalization with up to 16 dB of high-frequency gain EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

■ On-die power supply regulators for transmitter and receiver phase-locked loop (PLL) charge pump and voltage controlled oscillator (VCO) for superior noise immunity

■ On-package and on-chip power supply decoupling to satisfy transient current requirements at higher frequencies, thereby reducing the need for on-board decoupling capacitors

■ Calibration circuitry for transmitter and receiver on-chip termination (OCT)

Resistors EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

 

FPGA Fabric and I/O Features

The following section describes the Stratix IV FPGA fabric and I/O features.

Device Core Features

■ Up to 531,200 LEs in Stratix IV GX and Stratix IV GT devices and up to 813,050 Les in Stratix IV E devices, efficiently packed in unique and innovative adaptive logic modules (ALMs)

■ Ten ALMs per logic array block (LAB) deliver faster performance, improved logic utilization, and optimized routing EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

■ Programmable power technology, including a variety of process, circuit, and architecture optimizations and innovations

■ Programmable power technology available to select power-driven compilation options for reduced static power consumption Embedded Memory

■ TriMatrix embedded memory architecture provides three different memory block sizes to efficiently address the needs of diversified FPGA designs: EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

■ 640-bit MLAB

■ 9-Kbit M9K

■ 144-Kbit M144K

■ Up to 33,294 Kbit of embedded memory operating at up to 600 MHz

■ Each memory block is independently configurable to be a single- or dual-port RAM, FIFO, ROM, or shift register Digital Signal Processing (DSP) Blocks EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

■ Flexible DSP blocks configurable as 9 × 9-bit, 12 × 12-bit, 18 × 18-bit, and 36 × 36-bit full-precision multipliers at up to 600 MHz with rounding and

saturation capabilities

■ Faster operation due to fully pipelined architecture and built-in addition, subtraction, and accumulation units to combine multiplication results EP4SGX530F1517 Altera IC Stratix IV Transceiver FPGA 530K FBGA1517

■ Optimally designed to support advanced features such as adaptive filtering, barrel shifters, and finite and infinite impulse response (FIR and IIR) filters Clock Networks

■ Up to 16 GCLKs and 88 RCLKs optimally routed to meet the maximum performance of 800 MHz

■ Up to 112 and 132 PCLKs in Stratix IV GX and Stratix IV E devices, respectively

■ Up to 66 (16 GCLK + 22 RCLK + 28 PCLK) clock networks per device quadrant in

Stratix IV GX and Stratix IV GT devices

■ Up to 71 (16 GCLK + 22 RCLK + 33 PCLK) clock networks per device quadrant in

Stratix IV E devices