Configuration Devices
■ Configuration device family for configuring Altera? ACEX? 1K, APEX? 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria? GX, Cyclone?, Cyclone II, FLEX? 10K (including FLEX 10KE and FLEX 10KA)Mercury?, Stratix?, Stratix GX, Stratix II, and Stratix II GX devices. EP224DM883B-20N Altera IC Classic EPLD
■ Easy-to-use 4-pin interface to Altera FPGAs
■ Low current during configuration and near-zero standby current
■ 5.0-V and 3.3-V operation EP224DM883B-20N Altera IC Classic EPLD
■ Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
■ Available in compact plastic packages EP224DM883B-20N Altera IC Classic EPLD
■ 8-pin plastic dual in-line package (PDIP)
■ 20-pin plastic J-lead chip carrier (PLCC) package EP224DM883B-20N Altera IC Classic EPLD
■ 32-pin plastic thin quad flat pack (TQFP) package
■ EPC2 device has reprogrammable Flash configuration memory
■ 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
■ Supports programming through Serial Vector Format Files (.svf), Jam? Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), and the Quartus? II and MAX+PLUS? II softwares via the USB Blaster, MasterBlaster?, ByteBlaster? II, EthernetBlaster, or ByteBlasterMV? download cable EP224DM883B-20N Altera IC Classic EPLD
■ nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration
■ Can be programmed with Programmer Object Files (.pof) for EPC1 and EPC1441 devices
■ Available in 20-pin PLCC and 32-pin TQFP packages
Functional Description
With SRAM-based devices, configuration data must be reloaded each time the device powers up, the system initializes, or when new configuration data is needed. EP224DM883B-20N Altera IC Classic EPLD Altera configuration devices store configuration data for SRAM-based ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices. Table 4–1 lists Altera configuration devices and their features. EP224DM883B-20N Altera IC Classic EPLD
The configuration device’s OE and nCS pins control the tri-state buffer on its DATA output pin, and enable the address counter and oscillator. When OE is driven low, the configuration device resets the address counter and tri-states its DATA pin. The nCS pin controls the DATA output of the configuration device. EP224DM883B-20N Altera IC Classic EPLD If nCS is held high after the OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. If nCS is driven low after the OE reset pulse, the counter and DATA output pin are enabled. When OE is driven low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of nCS. If the FPGA’s configuration data exceeds the capacity of a single EPC1 or EPC2 configuration device, multiple EPC1 or EPC2 devices can be cascaded together. EP224DM883B-20N Altera IC Classic EPLD If multiple EPC1 or EPC2 devices are required, the nCASC and nCS pins provide handshaking between the configuration devices. 1 EPC1441 and EPC1064/V devices cannot be cascaded.When configuring ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices with cascaded EPC1 or EPC2 devices, the position of the EPC1 or EPC2 device in the chain determines its mode of operation. The first configuration device in the chain is the master, while subsequent configuration devices are slaves. The nINIT_CONF pin of the master EPC2 device can be connected to the nCONFIG of the FPGAs, which allows the INIT_CONF JTAG instruction to begin FPGA configuration. The nCS pin of the master configuration device is connected to the CONF_DONE of the FPGAs, EP224DM883B-20N Altera IC Classic EPLD while its nCASC pin is connected to nCS of the next slave configuration device in the chain. Additional EPC1 or EPC2 devices can be chained together by connecting nCASC to nCS of the next slave EPC1 or EPC2 device in the chain. The last device’s nCS input comes from the previous device, while its nCASC pin is left floating. All other configuration pins (DCLK, DATA, and OE) are connected to every device in the chain. Figure 4–3 shows the basic configuration interface connections between a configuration device chain and the Altera FPGA. f For specific details about configuration interface connections, including pull-up resistor values, supply voltages and MSEL pin setting, refer to the appropriate FPGA family chapter in the Configuration Handbook EP224DM883B-20N Altera IC Classic EPLD
3.3-V or 5.0-V Operation
The EPC1, EPC2, and EPC 1441 configuration device may be powered at 3.3 V or 5.0 V. For each configuration device, an option must be set for 5.0-V or 3.3-V operation.For EPC1 and EPC1441 configuration devices, EP224DM883B-20N Altera IC Classic EPLD 3.3-V or 5.0-V operation is controlled by a programming bit in the .pof. The Low-Voltage mode option in the Options tab of the Configuration Device Options dialog box in the Quartus II software or the Use Low-Voltage Configuration EPROM option in the Global Project Device Options dialog box (Assign menu) in the MAX+PLUS II software sets this parameter. EP224DM883B-20N Altera IC Classic EPLD For example, EPC1 devices are programmed automatically to operate in 3.3-V mode when configuring FLEX 10KA devices, which have a VCC voltage of 3.3 V. In this example, the EPC1 device’s VCC pin is connected to a 3.3-V power supply.