MAX 7000A Device

EPM7256AEQI208-10N Altera IC MAX 7000A CPLD 256 PQFP208

Feature :

EPM7032AE   EPM7064AE   EPM7128AE

EPM7256AE   EPM7512AE

EPM7256AEQI208-10N Altera IC MAX 7000A CPLD 256 PQFP208

Features...

EPM7256AEQI208-10N Altera IC MAX 7000A CPLD 256 PQFP208

■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX?) architecture (see Table 1)

■ 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability

– MAX 7000Adevices  device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532

– EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532

■ Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1

■ Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71

■ Enhanced ISP features

– Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices)

– ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices)

– Pull-up resistor on I/O pins during in-system programming

■ Pin-compatible with the popular 5.0-V MAX 7000S devices

■ High-density PLDs ranging from 600 to 10,000 usable gates

■ Extended temperature range

EPM7256AEQI208-10N Altera IC MAX 7000A CPLD 256 PQFP208

General Description

MAX 7000Adevices  (including MAX 7000AE) devices are high-density, highperformance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification. EPM7256AEQI208-10N Altera IC MAX 7000A CPLD 256 PQFP208

The MAX 7000Adevices architecture supports 100% transistor-to-transistor logic (TTL) emulation and high-density integration of SSI, MSI, and LSI logic functions. It easily integrates multiple devices including PALs, GALs, and 22V10s devices. MAX 7000A devices are available in a wide range of

packages, including PLCC, BGA, FineLine BGA, Ultra FineLine BGA, PQFP, and TQFP packages.EPM7256AEQI208-10N Altera IC MAX 7000A CPLD 256 PQFP208

MAX 7000A devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations

during design development and debug cycles, and can be programmed and erased up to 100 times.

EPM7256AEQI208-10N Altera IC MAX 7000A CPLD 256 PQFP208

MAX 7000A devices contain from 32 to 512 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). EPM7256AEQI208-10N Altera IC MAX 7000A CPLD 256 PQFP208. Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and highspeed parallel expander product terms, providing up to 32 product terms per macrocell.  MAX 7000Adevices provide programmable speed/power optimization. Speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 7000A devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. The output drivers of all MAX 7000Adevices can be set for 2.5 V or 3.3 V, and all input pins are 2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 7000A devices to be used in mixed-voltage systems.  EPM7256AEQI208-10N Altera IC MAX 7000A CPLD 256 PQFP208

Functional Description

EPM7256AEQI208-10N Altera IC MAX 7000A CPLD 256 PQFP208

The MAX 7000A architecture includes the following elements:

■ Logic array blocks (LABs)

■ Macrocells

■ Expander product terms (shareable and parallel)

■ Programmable interconnect array

■ I/O control blocks

EPM7256AEQI208-10N Altera IC MAX 7000A CPLD 256 PQFP208

The MAX 7000Adevices  architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of MAX 7000A devices.