EPM9480C208-20N Altera IC MAX 9000 CPLD 480

 

EPM9480C208-20N Altera IC MAX 9000 CPLD 480

 

High-performanceMAX 9000  CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX EPM9480C208-20N Altera IC MAX 9000 CPLD 480.5.0-V in-system programmability (ISP) through built-in IEEE Std.1149.1 Joint Test Action Group (JTAG) interface n Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 n High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates (see Table 1)

 

10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz Fully compliant with the peripheral component interconnect Special Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2

 

Dual-output macrocell for independent use of combinatorial and registered logic FastTrack Interconnect for fast, predictable interconnect delays Input/output registers with clear and clock enable on all I/O pins Programmable output slew-rate control to reduce switching noise MultiVolt

I/O interface operation, allowing devices to interface with 3.3-V and 5.0-V devices

Configurable expander product-term distribution allowing up to 32 product terms per macrocell

Programmable power-saving mode for more than 50% power reduction in each macrocell

EPM9480C208-20N Altera IC MAX 9000 CPLD 480 .The MAX 9000 family of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed grade of the MAX 9000 family is compliant with the PCI Local Bus Specification,EPM9480C208-20N Altera IC MAX 9000 CPLD 480.The MAX 9000 architecture supports high-density integration of systemlevel logic functions. It easily integrates multiple programmable logic devices ranging from PALs, GALs, and 22V10s to field-programmable gate array (FPGA) devices and EPLDs EPM9480C208-20N Altera IC MAX 9000 CPLD 480.All MAX 9000 device packages provide four dedicated inputs for global control signals with large fan-outs. Each I/O pin has an associated I/O cell register with a clock enable control on the periphery of the device. As outputs, these registers provide fast clock-to-output times; as inputs, they offer quick setup times. EPM9480C208-20N Altera IC MAX 9000 CPLD 480 .MAX 9000 EPLDs provide 5.0-V in-system programmability (ISP). This feature allows the devices to be programmed and reprogrammed on the printed circuit board (PCB) for quick and efficient iterations during design development and debug cycles. MAX 9000 devices are guaranteed for 100 program and erase cycles.

EPM9480C208-20N Altera IC MAX 9000 CPLD 480

 

EPM9480C208-20N Altera IC MAX 9000 CPLD 480

MAX 9000 devices use a third-generation MAX architecture that yields both high performance and a high degree of utilization for most applications. The MAX 9000 architecture includes the following elements: Logic array blocks Macrocells Expander product terms (shareable and parallel)FastTrack Interconnect Dedicated inputs I/O cells EPM9480C208-20N Altera IC MAX 9000 CPLD 480.Timing Model The continuous, high-performance FastTrack Interconnect ensures predictable performance and accurate simulation and timing analysis.This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and hence have unpredictable performance. Timing simulation and delay prediction are available with the MAX+PLUS II Simulator and Timing Analyzer, or with industrystandard EDA tools. The Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post-synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer provides pointto- point timing delay information, setup and hold time prediction, and device-wide performance analysis. EPM9480C208-20N Altera IC MAX 9000 CPLD 480 The MAX 9000 timing model in Figure 14 shows the delays that correspond to various paths and functions in the circuit. This model contains three distinct parts: the macrocell, IOC, and interconnect, including the row and column FastTrack Interconnect and LAB local array paths. Each parameter shown in Figure 14 is expressed as a worst-case value in the internal timing characteristics tables in this data sheet. Handcalculations that use the MAX 9000 timing model and these timing parameters can be used to estimate MAX 9000 device performance. EPM9480C208-20N Altera IC MAX 9000 CPLD 480