EP20K100BC356-1VN Altera IC APEX 20K FPGA 100K BGA356

 

Features

■ Industry’s first programmable logic device (PLD) incorporating system-on-a-programmable-chip (SOPC) integration

– MultiCoreTM architecture integrating look-up table (LUT) logic,product-term logic, and embedded memory

– LUT logic used for register-intensive functions

– Embedded system block (ESB) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM)

– ESB implementation of product-term logic used for combinatorial-intensive functions

■ High density

– 30,000 to 1.5 million typical gates (see Tables 1 and 2)

– Up to 51,840 logic elements (LEs)

– Up to 442,368 RAM bits that can be used without reducing available logic

– Up to 3,456 product-term-based macrocells

EP20K100BC356-1VN Altera IC APEX 20K FPGA 100K BGA356

 

APEXTM 20K devices are the first PLDs designed with the MultiCore architecture, which combines the strengths of LUT-based and productterm-based devices with an enhanced memory structure. LUT-based logic provides optimized performance and efficiency for data-path, registerintensive,mathematical, or digital signal processing (DSP) designs.EP20K100BC356-1VN Altera IC APEX 20K FPGA 100K BGA356.Product-term-based logic is optimized for complex combinatorial paths,such as complex state machines. LUT- and product-term-based logic

combined with memory functions and a wide variety of MegaCore and AMPP functions make the APEX 20K device architecture uniquely suited for system-on-a-programmable-chip designs. Applications historically requiring a combination of LUT-, product-term-, and memory-based

devices can now be integrated into one APEX 20K device.

EP20K100BC356-1VN Altera IC APEX 20K FPGA 100K BGA356

APEX 20KE devices are a superset of APEX 20K devices and include additional features such as advanced I/O standard support, CAM,additional global clocks, and enhanced ClockLock clock circuitry. EP20K100BC356-1VN Altera IC APEX 20K FPGA 100K BGA356.In addition, APEX 20KE devices extend the APEX 20K family to 1.5 million gates. APEX 20KE devices are denoted with an “E” suffix in the device name (e.g., the EP20K1000E device is an APEX 20KE device). Table 8 compares the features included in APEX 20K and APEX 20KE devices.EP20K100BC356-1VN Altera IC APEX 20K FPGA 100K BGA356.All APEX 20K devices are reconfigurable and are 100% tested prior to shipment. As a result, test vectors do not have to be generated for fault

coverage purposes.EP20K100BC356-1VN Altera IC APEX 20K FPGA 100K BGA356.Instead, the designer can focus on simulation and design verification. EP20K100BC356-1VN Altera IC APEX 20K FPGA 100K BGA356 In addition, the designer does not need to manage inventories of different application-specific integrated circuit (ASIC)designs; APEX 20K devices can be configured on the board for the specific functionality required. APEX 20K devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller.Altera offers in-system programmability (ISP)-capable EPC1, EPC2, and EPC16 configuration devices, which configure APEX 20K devices via a serial data stream. EP20K100BC356-1VN Altera IC APEX 20K FPGA 100K BGA356 Moreover, APEX 20K devices contain an optimized interface that permits microprocessors to configure APEX 20K devices serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat APEX 20K devices as memory and configure the device by writing to a virtual memory location, making reconfiguration easy.

EP20K100BC356-1VN Altera IC APEX 20K FPGA 100K BGA356.After an APEX 20K device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Real-time changes can be made during system operation, enabling innovative reconfigurable computing applications.

EP20K100BC356-1VN Altera IC APEX 20K FPGA 100K BGA356.APEX 20K devices are supported by the Altera Quartus II development system, a single, integrated package that offers HDL and schematic design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, SignalTap logic analysis, and device configuration. The Quartus II software runs on Windows-based PCs, Sun SPARCstations,and HP 9000 Series 700/800 workstations.EP20K100BC356-1VN Altera IC APEX 20K FPGA 100K BGA356.The Quartus II software provides NativeLink interfaces to other industrystandard.PC- and UNIX workstation-based EDA tools. For example,designers can invoke the Quartus II software from within third-party design tools. Further, the Quartus II software contains built-in optimized synthesis libraries; synthesis tools can use these libraries to optimize designs for APEX 20K devices. For example, the Synopsys Design Compiler library, supplied with the Quartus II development system,includes DesignWare functions optimized for the APEX 20K architecture.EP20K100BC356-1VN Altera IC APEX 20K FPGA 100K BGA356

 

APEX 20K devices incorporate LUT-based logic, product-term-based logic, and memory into one device. Signal interconnections within APEX 20K devices (as well as to and from device pins) are provided by the FastTrack? Interconnect—a series of fast, continuous row and column channels that run the entire length and width of the device.Each I/O pin is fed by an I/O element (IOE) located at the end of each row and column of the FastTrack Interconnect. Each IOE contains a bidirectional I/O buffer and a register that can be used as either an input or output register to feed input, output, or bidirectional signals. When used with a dedicated clock pin, these registers provide exceptional performance. IOEs provide a variety of features, such as 3.3-V, 64-bit,

66-MHz PCI compliance; JTAG BST support; slew-rate control; and tri-state buffers. EP20K100BC356-1VN Altera IC APEX 20K FPGA 100K BGA356.APEX 20KE devices offer enhanced I/O support,including support for 1.8-V I/O, 2.5-V I/O, LVCMOS, LVTTL, LVPECL,3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3, HSTL, CTT, and 3.3-V.AGP I/O standards.