EP20K30EQC208-3X Altera IC APEX 20KE FPGA 30K PQFP208

 

EP20K30EQC208-3X Altera IC APEX 20KE FPGA 30K PQFP208

■Industry’s first programmable logic device (PLD) incorporating system-on-a-programmable-chip (SOPC) integration

– MultiCoreTM architecture integrating look-up table (LUT) logic,product-term logic, and embedded memory

– LUT logic used for register-intensive functions

– Embedded system block (ESB) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM)

– ESB implementation of product-term logic used for combinatorial-intensive functions

■ High density

– 30,000 to 1.5 million typical gates (see Tables 1 and 2)

– Up to 51,840 logic elements (LEs)

– Up to 442,368 RAM bits that can be used without reducing available logic

– Up to 3,456 product-term-based macrocells

EP20K30EQC208-3X Altera IC APEX 20KE FPGA 30K PQFP208

 

APEXTM 20K devices are the first PLDs designed with the MultiCore architecture, which combines the strengths of LUT-based and productterm-based devices with an enhanced memory structure. LUT-based logic provides optimized performance and efficiency for data-path, registerintensive,mathematical, or digital signal processing (DSP) designs.EP20K30EQC208-3X Altera IC APEX 20KE FPGA 30K PQFP208.Product-term-based logic is optimized for complex combinatorial paths,such as complex state machines. LUT- and product-term-based logic

combined with memory functions and a wide variety of MegaCore and AMPP functions make the APEX 20K device architecture uniquely suited for system-on-a-programmable-chip designs. Applications historically.requiring a combination of LUT-, product-term-, and memory-based devices can now be integrated into one APEX 20K device. EP20K30EQC208-3X Altera IC APEX 20KE FPGA 30K PQFP208.APEX 20KE devices are a superset of APEX 20K devices and include additional features such as advanced I/O standard support, CAM,additional global clocks, and enhanced ClockLock clock circuitry. EP20K30EQC208-3X Altera IC APEX 20KE FPGA 30K PQFP208

In addition, APEX 20KE devices extend the APEX 20K family to 1.5 million gates. APEX 20KE devices are denoted with an “E” suffix in the device name (e.g., the EP20K1000E device is an APEX 20KE device). Table 8 compares the features included in APEX 20K and APEX 20KE devices. EP20K30EQC208-3X Altera IC APEX 20KE FPGA 30K PQFP208

All APEX 20K devices are reconfigurable and are 100% tested prior to shipment. As a result, test vectors do not have to be generated for fault coverage purposes. EP20K30EQC208-3X Altera IC APEX 20KE FPGA 30K PQFP208.Instead, the designer can focus on simulation and design verification. In addition, the designer does not need to manage inventories of different application-specific integrated circuit (ASIC)designs; APEX 20K devices can be configured on the board for the specific functionality required. EP20K30EQC208-3X Altera IC APEX 20KE FPGA 30K PQFP208

 

APEX 20K devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller.EP20K30EQC208-3X Altera IC APEX 20KE FPGA 30K PQFP208

Altera offers in-system programmability (ISP)-capable EPC1, EPC2, and EPC16 configuration devices, which configure APEX 20K devices via a serial data stream. Moreover, APEX 20K devices contain an optimized interface that permits microprocessors to configure APEX 20K devices serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat APEX 20K devices as memory and configure the device by writing to a virtual memory location, making reconfiguration easy. EP20K30EQC208-3X Altera IC APEX 20KE FPGA 30K PQFP208

After an APEX 20K device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Real-time changes can be made during system operation, enabling innovative reconfigurable computing applications. EP20K30EQC208-3X Altera IC APEX 20KE FPGA 30K PQFP208

 

APEX 20K devices are supported by the Altera Quartus II development system, a single, integrated package that offers HDL and schematic design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, SignalTap logic analysis, and device configuration. The Quartus II software runs on Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations.EP20K30EQC208-3X Altera IC APEX 20KE FPGA 30K PQFP208 .The Quartus II software provides NativeLink interfaces to other industrystandard PC- and UNIX workstation-based EDA tools. For example, designers can invoke the Quartus II software from within third-party design tools. Further, the Quartus II software contains built-in optimized synthesis libraries; synthesis tools can use these libraries to optimize designs for APEX 20K devices. For example, the Synopsys Design

Compiler library, supplied with the Quartus II development system,includes DesignWare functions optimized for the APEX 20K architecture. EP20K30EQC208-3X Altera IC APEX 20KE FPGA 30K PQFP208.The APEX 20K architecture supports several configuration schemes. This section summarizes the device operating modes and available device configuration schemes.

 

EP20K30EQC208-3X Altera IC APEX 20KE FPGA 30K PQFP208

The APEX architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called configuration. During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up,and before and during configuration. Together, the configuration and initialization processe