EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256

 

 

Features...

EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256

■ The industry’s first embedded programmable logic device (PLD)family, providing System-on-a-Programmable-Chip (SOPC) integration

– Embedded array for implementing megafunctions, such as efficient memory and specialized logic functions

– Logic array for general logic functions

■ High density

– 10,000 to 250,000 typical gates (see Tables 1 and 2)

– Up to 40,960 RAM bits; 2,048 bits per embedded array block (EAB), all of which can be used without reducing logic capacity

■ System-level features

– MultiVoltTM I/O interface support

– 5.0-V tolerant input pins in FLEX? 10KA devices

– Low power consumption (typical specification less than 0.5 mA in standby mode for most devices)

– FLEX 10K and FLEX 10KA devices support peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2

– FLEX 10KA devices include pull-up clamping diode, selectable on a pin-by-pin basis for 3.3-V PCI compliance

– Select FLEX 10KA devices support 5.0-V PCI buses with eight or fewer loads

– Built-in Joint Test Action Group (JTAG) boundary-scan test

(BST) circuitry compliant with IEEE Std. 1149.1-1990, available

without consuming any device logic EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256.Signal interconnections within FLEX 10K devices and to and from device pins are provided by the FastTrack Interconnect, a series of fast,continuous row and column channels that run the entire length and width of the device.

EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256

Each I/O pin is fed by an I/O element (IOE) located at the end of each row and column of the FastTrack Interconnect. EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256.Each IOE contains a bidirectional I/O buffer and a flipflop that can be used as either an output or input register to feed input, output, or bidirectional signals. When used with a dedicated clock pin, these registers provide exceptional performance. EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256

As inputs, they provide setup times as low as 1.6 ns and hold times of 0 ns; as outputs, these registers provide clock-to-output times as low as 5.3 ns. IOEs provide a variety of features, such as JTAG BST support, slew-rate control, tri-state buffers, and open-drain outputs.Figure 1 shows a block diagram of the FLEX 10K architecture. Each group of LEs is combined into an LAB; LABs are arranged into rows and columns. EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256.Each row also contains a single EAB. The LABs and EABs are interconnected by the FastTrack Interconnect. IOEs are located at the end of each row and column of the FastTrack Interconnect.EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256.Each of these modes uses LE resources differently. In each mode, seven available inputs to the LE—the four data inputs from the LAB local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous LE—are directed to different destinations to implement the desired logic function. Three inputs to the LE provide clock, clear, and preset control for the register. The Altera

software, in conjunction with parameterized functions such as LPM and DesignWare functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers. If required,the designer can also create special-purpose functions which use a specific

LE operating mode for optimal performance.EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256.The architecture provides a synchronous clock enable to the register in all four modes. The Altera software can set DATA1 to enable the register synchronously, providing easy implementation of fully synchronous designs. EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256

 

In the FLEX 10K architecture, connections between LEs and device I/O pins are provided by the FastTrack Interconnect, which is a series of continuous horizontal and vertical routing channels that traverse the device. This global routing structure provides predictable performance,

even in complex designs.EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256

 In contrast, the segmented routing in FPGAs requires switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance. The FastTrack Interconnect consists of row and column interconnect channels that span the entire device. Each row of LABs is served by a dedicated row interconnect. The row interconnect can drive I/O pins and feed other LABs in the device. The column interconnect routes signals between rows and can drive I/O pins.EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256.A row channel can be driven by an LE or by one of three column channels.These four signals feed dual 4-to-1 multiplexers that connect to two specific row channels. These multiplexers, which are connected to each LE, allow column channels to drive row channels even when all eight Les in an LAB drive the row interconnect.EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256.Each column of LABs is served by a dedicated column interconnect. The column interconnect can then drive I/O pins or another row’s interconnect to route the signals to other LABs in the device. A signal from the column interconnect, which can be either the output of an LE or an input from an I/O pin, must be routed to the row interconnect before it can enter an LAB or EAB. Each row channel that is driven by an IOE or EAB can drive one specific column channel. EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256

Access to row and column channels can be switched between LEs in adjacent pairs of LABs. For example, an LE in one LAB can drive the row and column channels normally driven by a particular LE in the adjacent LAB in the same row, and vice versa. This routing flexibility enables

routing resources to be used more efficiently.EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256

 

FLEX 10KE devices support the SameFrame pin-out feature for FineLine BGA packages. The SameFrame pin-out feature is the arrangement of balls on FineLine BGA packages such that the lower-ballcount packages form a subset of the higher-ball-count packages. SameFrame pin-outs provide the flexibility to migrate not only from device to device within the same package, but also from one package to another. A given printed circuit board (PCB) layout can support multiple

device density/package combinations. For example, a single board layout can support a range of devices from an EPF10K10A device in a 256-pin FineLine BGA package to an EPF10K100A device in a 484-pin FineLine BGA package.EPF10K30ABC256-3N Altera IC FLEX 10KA FPGA 30K BGA256.The Altera software provides support to design PCBs with SameFrame pin-out devices. Devices can be defined for present and future use. The Altera software generates pin-outs describing how to lay out a board to take advantage of this migration