EP1M120B484C8AN Altera IC Mercury FPGA 120K BGA484

 

 

EP1M120B484C8AN Altera IC Mercury FPGA 120K BGA484

Mercury devices integrate high-speed differential transceivers and support for CDR with a speed-optimized PLD architecture. These transceivers are implemented through the dedicated serializer, deserializer, and clock recovery circuitry in the HSDI and incorporate support for the LVDS, LVPECL, and 3.3-V PCML I/O standards. EP1M120B484C8AN Altera IC Mercury FPGA 120K BGA484.This circuitry, together with enhanced I/O elements (IOEs) and support for numerous I/O standards, allows Mercury devices to meet high-speed interface requirements.EP1M120B484C8AN Altera IC Mercury FPGA 120K BGA484.Mercury devices are the first PLDs optimized for core performance. These LUT-based, enhanced memory devices use a network of fast routing resources to achieve optimal performance. These resources are ideal for data-path, register-intensive, mathematical, digital signal processing(DSP), or communications designs.

EP1M120B484C8AN Altera IC Mercury FPGA 120K BGA484

 

Mercury devices include other features for performance such as quadport RAM, CAM, general purpose PLLs, and dedicated circuitry for implementing multiplier circuits. Table 4 shows Mercury performance.

 

EP1M120B484C8AN Altera IC Mercury FPGA 120K BGA484

The logic, circuitry, and interconnects in the Mercury architecture are configured with CMOS SRAM elements. Mercury devices are reconfigurable and are 100% tested prior to shipment. As a result, test vectors do not have to be generated for fault coverage purposes. Instead,the designer can focus on simulation and design verification. In addition, the designer does not need to manage inventories of different ASIC designs; Mercury devices can be configured on the board for the specific

EP1M120B484C8AN Altera IC Mercury FPGA 120K BGA484.Mercury devices are configured at system power-up with data stored in an Altera? serial configuration device or provided by a system controller.Altera offers in-system programmability (ISP)-capable configuration devices, which configure Mercury devices via a serial data stream.Mercury devices can be configured in under 70 ms.

EP1M120B484C8AN Altera IC Mercury FPGA 120K BGA484

 Moreover, Mercury devices contain an optimized interface that permits microprocessors to

configure Mercury devices serially or in parallel, synchronously or asynchronously. This interface also enables microprocessors to treat Mercury devices as memory and to configure the device by writing to a virtual memory location, simplifying reconfiguration EP1M120B484C8AN Altera IC Mercury FPGA 120K BGA484

 

Mercury devices are supported by the Altera QuartusTM II development system, a single, integrated package that offers HDL and schematic design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, SignalTapTM logic analysis, and device configuration. The Quartus II software also ships with Altera-specific HDL synthesis tools from Exemplar Logic and Synopsys, and Altera-specific Register Transfer Level (RTL) and timing simulation tools from Model Technology. The Quartus II software supports PCs running Windows 98, Windows NT 4.0,and Windows 2000; UNIX workstations running Solaris 2.6, 7, or 8, or

HP-UX 10.2 or 11.0; and PCs running Red Hat Linux 7.1.The Quartus II software provides NativeLinkTM interfaces to other industry-standard PC- and UNIX-workstation-based EDA tools. For example, designers can invoke the Quartus II software from within the Mentor Graphics LeonardoSpectrum software, Synplicity’s Synplify software, and the Synopsys FPGA Express software. The Quartus II software also contains built-in optimized synthesis libraries; synthesis

tools can use these libraries to optimize designs for Mercury devices. For example, the Synopsys Design Compiler library, supplied with the Quartus II development system, includes DesignWare functions optimized for the Mercury architecture. For more information on the Quartus II development system, see the Quartus II Programmable Logic Development System & Software Data Sheet.EP1M120B484C8AN Altera IC Mercury FPGA 120K BGA484

 

The Mercury architecture contains a row-based logic array to implement general logic and a row-based embedded system array to implement memory and specialized logic functions. Signal interconnections within Mercury devices are provided by a series of row and column interconnects with varying lengths and speeds. The priority FastTrack Interconnect structure is faster than other interconnects; the Quartus II Compiler places design-critical paths on these faster lines to improve

design performance. EP1M120B484C8AN Altera IC Mercury FPGA 120K BGA484.Mercury device I/O pins are evenly distributed across the entire device area; other Altera device families have I/O pins placed on the device periphery.EP1M120B484C8AN Altera IC Mercury FPGA 120K BGA484. Mercury device I/O pin placement allows for higher I/O count at a given die size; pad size is no longer a limiting issue. Each I/O pin is fed by an IOE.  EP1M120B484C8AN Altera IC Mercury FPGA 120K BGA484

IOEs are grouped in IOE row bands from the top to the bottom of the device. IOE row bands are separated by several LAB rows.LABs from the associated LAB row closest to the I/O row band drive IOEs through the local interconnect. This feature allows fast clock-to-output times when a pin is driven by any of the 10 LEs in the adjacent associated LAB. Each IOE contains a bidirectional buffer along with an input register,output register, output enable (OE) register, and input latch for DDR.EP1M120B484C8AN Altera IC Mercury FPGA 120K BGA484.When used with a global clock, these dedicated registers provide exceptional bidirectional I/O performance.