Stratix GX
EP1SGX10 EP1SGX25 EP1SGX40
EP1SGX25DF672I7N Altera IC STRATIX GX FPGA 25KLE FBGA672
Overview The Stratix? GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES capability at data rates of up to 3.1875 gigabits per second (Gbps). EP1SGX25DF672I7N Altera IC STRATIX GX FPGA 25KLE FBGA672
These transceivers are grouped by four-channel transceiver blocks, and are designed for low power consumption and small die size. The Stratix GX FPGA technology is built upon the Stratix architecture, and offers a 1.5-V logic array with unmatched performance,flexibility, and time-to-market capabilities. This scalable,high-performance architecture makes Stratix GX devices ideal for high-speed backplane interface, chip-to-chip, and communications protocol-bridging applications.EP1SGX25DF672I7N Altera IC STRATIX GX FPGA 25KLE FBGA672
Features
■ Transceiver block features are as follows: EP1SGX25DF672I7N Altera IC STRATIX GX FPGA 25KLE FBGA672
● High-speed serial transceiver channels with CDR provides 500-megabits per second (Mbps) to 3.1875-Gbps full-duplex
operation
● Devices are available with 4, 8, 16, or 20 high-speed serial transceiver channels providing up to 127.5 Gbps of full-duplex serial bandwidth
● Support for transceiver-based protocols, including 10 Gigabit Ethernet attachment unit interface (XAUI), Gigabit Ethernet (GigE), and SONET/SDH
● Compatible with PCI Express, SMPTE 292M, Fibre Channel, and Serial RapidIO I/O standards
● Programmable differential output voltage (VOD), pre-emphasis,and equalization settings for improved signal integrity
● Individual transmitter and receiver channel power-down capability implemented automatically by the Quartus? II software for reduced power consumption during non-operation
● Programmable transceiver-to-FPGA interface with support for 8-, 10-, 16-, and 20-bit wide data paths
● 1.5-V pseudo current mode logic (PCML) for 500 Mbps to3.1875 Gbps
● Support for LVDS, LVPECL, and 3.3-V PCML on reference clocks and receiver input pins (AC-coupled)
● Built-in self test (BIST)
● Hot insertion/removal protection circuitry.EP1SGX25DF672I7N Altera IC STRATIX GX FPGA 25KLE FBGA672
Functional Description
EP1SGX25DF672I7N Altera IC STRATIX GX FPGA 25KLE FBGA672
The Stratix GX device family supports high-speed serial transceiver blocks with CDR circuitry as well as source-synchronous interfaces. EP1SGX25DF672I7N Altera IC STRATIX GX FPGA 25KLE FBGA672 The channels on the right side of the device use an embedded circuit dedicated for receiving and transmitting high-speed serial data streams to and from the system board. EP1SGX25DF672I7N Altera IC STRATIX GX FPGA 25KLE FBGA672. These channels are clustered in a four-channel serial transceiver building block and deliver high-speed bidirectional point-to-point data transmissions to provide up to 3.1875 Gbps of full-duplex data transmission per channel. EP1SGX25DF672I7N Altera IC STRATIX GX FPGA 25KLE FBGA672
The channels on the left side of the device support source-synchronous data transfers at up to 1 Gbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O standards. Figure 1–1 shows the Stratix GX I/O blocks.The differential source-synchronous serial interface and the high-speed serial interface are described in the Stratix GX Transceivers chapter of the Stratix GX Device Handbook EP1SGX25DF672I7N Altera IC STRATIX GX FPGA 25KLE FBGA672 FPGA Functional
Description
Stratix GX devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provide signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks. EP1SGX25DF672I7N Altera IC STRATIX GX FPGA 25KLE FBGA672.The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of
user logic functions. LABs are grouped into rows and columns across the device. M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 318 MHz. M512 blocks are grouped into columns across the device in between certain LABs.M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 291 MHz.These blocks are grouped into columns across the device in between certain LABs.EP1SGX25DF672I7N Altera IC STRATIX GX FPGA 25KLE FBGA672 .Transceiver Blocks Stratix? GX devices incorporate dedicated embedded circuitry on the right side of the device, which contains up to 20 high-speed 3.1875-Gbps serial transceiver channels. Each Stratix GX transceiver block contains four full-duplex channels and supporting logic to transmit and receive high-speed serial data streams. The transceiver block uses the channels to deliver bidirectional point-to-point data transmissions with up to 3.1875 Gbps of data transition per channel. EP1SGX25DF672I7N Altera IC STRATIX GX FPGA 25KLE FBGA672