EP2S130F1020C3N Altera IC STRATIX II FPGA 130K FBGA1020

 

Introduction The Stratix? EP2S130F1020C3N Altera IC STRATIX II FPGA 130K FBGA1020 .II FPGA family is based on a 1.2-V, 90-nm, all-layer copper SRAM process and features a new logic structure that maximizes performance, and enables device densities approaching 180,000 equivalent logic elements (LEs). EP2S130F1020C3N Altera IC STRATIX II FPGA 130K FBGA1020.Stratix II devices offer up to 9 Mbits of on-chip, TriMatrix? memory for demanding, memory intensive applications and has up to 96 DSP blocks with up to 384 (18-bit × 18-bit)multipliers for efficient implementation of high performance filters and other DSP functions. Various high-speed external memory interfaces are supported, including double data rate (DDR) SDRAM and DDR2 SDRAM, RLDRAM II, quad data rate (QDR) II SRAM, and single data rate (SDR) SDRAM. Stratix II devices support various I/O standards along with support for 1-gigabit per second (Gbps) source synchronous signaling with DPA circuitry. Stratix II devices offer a complete clock management solution with internal clock frequency of up to 550 MHz and up to 12 phase-locked loops (PLLs). Stratix II devices are also the industry’s first FPGAs with the ability to decrypt a configuration bitstream using the Advanced Encryption Standard (AES) algorithm to protect designs. EP2S130F1020C3N Altera IC STRATIX II FPGA 130K FBGA1020

 

■ 15,600 to 179,400 equivalent LEs; see Table 1–1

■ New and innovative adaptive logic module (ALM), the basic building block of the Stratix II architecture, maximizes performance and resource usage efficiency

■ Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources

■ TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers

■ High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters

■ Up to 16 global clocks with 24 clocking resources per device region

■ Clock control blocks support dynamic clock network enable/disable,which allows clock networks to power down to reduce power consumption in user mode

■ Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover,real-time PLL reconfiguration, and advanced multiplication and phase shifting

■ Support for numerous single-ended and differential I/O standards

■ High-speed differential I/O support with DPA circuitry for 1-Gbps performance

■ Support for high-speed networking and communications bus standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY Level 4), HyperTransport? technology, and SFI-4

■ Support for high-speed external memory, including DDR and DDR2,SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM

■ Support for multiple intellectual property megafunctions from Altera MegaCore? functions and Altera Megafunction Partners Program (AMPPSM) megafunctions

■ Support for design security using configuration bitstream encryption

■ Support for remote configuration updates,EP2S130F1020C3N Altera IC STRATIX II FPGA 130K FBGA1020

 

Stratix,EP2S130F1020C3N Altera IC STRATIX II FPGA 130K FBGA1020

II devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provides signal interconnects between logic array blocks (LABs), memory block structures (M512 RAM,M4K RAM, and M-RAM blocks), and digital signal processing (DSP)blocks. EP2S130F1020C3N Altera IC STRATIX II FPGA 130K FBGA1020 Each LAB consists of eight adaptive logic modules (ALMs). An ALM is the Stratix II device family’s basic building block of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device.M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 500 MHz. M512 blocks are grouped into columns across the device in between certain LABs. M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 550 MHz. These blocks are grouped into columns across the device in between certain LABs.M-RAM blocks are true dual-port memory blocks with 512K bits plus parity (589,824 bits). These blocks provide dedicated true dual-port,simple dual-port, or single-port memory up to 144-bits wide at up to 420 MHz. Several M-RAM blocks are located individually in the device's logic array.EP2S130F1020C3N Altera IC STRATIX II FPGA 130K FBGA1020

 

EP2S130F1020C3N Altera IC STRATIX II FPGA 130K FBGA1020

In the Stratix II architecture, connections between ALMs, TriMatrix memory, DSP blocks, and device I/O pins are provided by the MultiTrack interconnect structure with DirectDriveTM technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for inter- and intra-design block connectivity.

EP2S130F1020C3N Altera IC STRATIX II FPGA 130K FBGA1020

 

The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance.DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement in the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycles that typically follow design changes and additions. EP2S130F1020C3N Altera IC STRATIX II FPGA 130K FBGA1020

 

Stratix II devices have a POR circuit to keep the whole device system in reset state until the power supply voltage levels have stabilized during power-up. The POR circuit monitors the VCCINT, VCCIO, and VCCPD voltage levels and tri-states all the user I/O pins while VCC is ramping up until normal user levels are reached. The POR circuitry also ensures that all eight I/O bank VCCIO voltages, VCCPD voltage, as well as the logic array VCCINT voltage, reach an acceptable level before configuration is triggered. After the Stratix II device enters user mode, the POR circuit continues to monitor the VCCINT voltage level so that a brown-out condition during user mode can be detected. If there is a VCCINT voltage sag below the Stratix II operational level during user mode, the POR circuit resets the device. EP2S130F1020C3N Altera IC STRATIX II FPGA 130K FBGA1020

When power is applied to a Stratix II device, a power-on-reset event occurs if VCC reaches the recommended operating range within a certain period of time (specified as a maximum VCC rise time). The maximum VCC rise time for Stratix II device is 100 ms. Stratix II devices provide a dedicated input pin (PORSEL) to select POR delay times of 12 or 100 ms during power-up. When the PORSEL pin is connected to ground, the POR time is 100 ms. When the PORSEL pin is connected to VCC, the POR time is 12 ms.