MAX II Feature
EPM240 EPM240G EPM570 EPM570G EPM1270 EPM1270G EPM2210
EPM2210G EPM240Z EPM570Z
EPM240GT100I5N Altera IC MAX II CPLD 240 LE TQFP100
Introduction
The MAX? II family of instant-on, non-volatile CPLDs is based on a 0.18-μm, 6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. EPM240GT100I5N Altera IC MAX II CPLD 240 LE TQFP100 MAX II devices offer high I/O counts, fast performance, and reliable fitting versus other CPLD architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system programmability (ISP), MAX II devices are designed to reduce cost and power while providing programmable solutions for applications such as bus bridging, I/O expansion, power-on reset (POR) and sequencing control, and device configuration control. EPM240GT100I5N Altera IC MAX II CPLD 240 LE TQFP100
Features
The MAX II CPLD has the following features:
■ Low-cost, low-power CPLD
■ Instant-on, non-volatile architecture EPM240GT100I5N Altera IC MAX II CPLD 240 LE TQFP100
■ Standby current as low as 25 μA EPM240GT100I5N Altera IC MAX II CPLD 240 LE TQFP100
■ Provides fast propagation delay and clock-to-output times
■ Provides four global clocks with two clocks available per logic array block (LAB)
■ UFM block up to 8 Kbits for non-volatile storage
■ MultiVolt core enabling external supply voltages to the device of either
3.3 V/2.5 V or 1.8 V EPM240GT100I5N Altera IC MAX II CPLD 240 LE TQFP100
■ MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels
■ Bus-friendly architecture including programmable slew rate, drive strength,
bus-hold, and programmable pull-up resistors
■ Schmitt triggers enabling noise tolerant inputs (programmable per pin)
■ I/Os are fully compliant with the Peripheral Component Interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V
operation at 66 MHz EPM240GT100I5N Altera IC MAX II CPLD 240 LE TQFP100
■ Supports hot-socketing
■ Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry
compliant with IEEE Std. 1149.1-1990
■ ISP circuitry compliant with IEEE Std. 1532
MAX II and MAX IIG devices are available in three speed grades: –3, –4, and –5, with –3 being the fastest. Similarly, MAX IIZ devices are available in three speed grades: –6,–7, and –8, with –6 being the fastest. EPM240GT100I5N Altera IC MAX II CPLD 240 LE TQFP100These speed grades represent the overall relative performance, not any specific timing parameter. For propagation delay timing numbers within each speed grade and density, refer to the DC and Switching Characteristics chapter in the MAX II Device Handbook. EPM240GT100I5N Altera IC MAX II CPLD 240 LE TQFP100
MAX II devices are available in space-saving FineLine BGA, Micro FineLine BGA, and thin quad flat pack (TQFP) packages (refer to Table 1–3 and Table 1–4). MAX II devices support vertical migration within the same package (for example, you can migrate between the EPM570, EPM1270, and EPM2210 devices in the 256-pin FineLine BGA package). EPM240GT100I5N Altera IC MAX II CPLD 240 LE TQFP100 Vertical migration means that you can migrate to devices whose dedicated pins and JTAG pins are the same and power pins are subsets or supersets for a given package across device densities. The largest density in any package has the highest number of power pins; you must lay out for the largest planned density in a package to provide the necessary power pins for migration. EPM240GT100I5N Altera IC MAX II CPLD 240 LE TQFP100 For I/O pin migration across densities, cross reference the available I/O pins using the device pin-outs for all planned densities of a given package type to identify which I/O pins can be migrated. The Quartus? II software can automatically cross-reference and place all pins for you when given a device migration list.
MAX II devices have an internal linear voltage regulator which supports external supply voltages of 3.3 V or 2.5 V, regulating the supply down to the internal operating voltage of 1.8 V. MAX IIG and MAX IIZ devices only accept 1.8 V as the external supply voltage. MAX IIZ devices are pin-compatible with MAX IIG devices in the 100-pin Micro FineLine BGA and 256-pin Micro FineLine BGA packages. Except for external supply voltage requirements, MAX II and MAX II G devices have identical pin-outs and timing specifications. Table 1–5 shows the external supply voltages supported by the MAX II family. EPM240GT100I5N Altera IC MAX II CPLD 240 LE TQFP100
MAX II devices have an internal linear voltage regulator which supports external supply voltages of 3.3 V or 2.5 V, EPM240GT100I5N Altera IC MAX II CPLD 240 LE TQFP100 regulating the supply down to the internal operating voltage of 1.8 V. MAX IIG and MAX IIZ devices only accept 1.8 V as the external supply voltage. EPM240GT100I5N Altera IC MAX II CPLD 240 LE TQFP100 MAX IIZ devices are pin-compatible with MAX IIG devices in the 100-pin Micro FineLine BGA and 256-pin Micro FineLine BGA packages. Except for external supply voltage requirements, MAX II and MAX II G devices have identical pin-outs and timing specifications. Table 1–5 shows the external supply voltages supported by the MAX II family. EPM240GT100I5N Altera IC MAX II CPLD 240 LE TQFP100