SAN FRANCISCO—Intellectual property (IP) reuse in SoC design is increasing, creating challenges in compatibility and complexity, according to executives on a Design Automation Conference (DAC) panel. To minimize this complexity, panelists said, the semiconductor industry will increasingly turn to IP subsystems—larger chunks of IP that have been stitched together from many smaller blocks and pre-verified to ensure performance.
Naveed Sherwani, president and CEO of chip design and manufacturing services provider Open-Silicon Inc., said he was happy to see that IP reuse was finally occurring on a large scale, but said the trend is creating challenges. Open-Silicon recently completed an SoC for a customer in which 60 percent of the silicon real estate was taken up by IP, including more than 100 different blocks from 16 different vendors, Sherwani said. He predicted that within two to three years some SoCs would be comprised of more than 80 percent reused IP.
"We should move away from just IPs to the direction of IP subsystems," Sherwani sad. "That is a very exciting area that I think you will see mature in the next two to three years."
John Koeter, vice president of marketing for Synopsys Inc.'s Solutions group, noted that Synopsys earlier this year introduced its first IP subsystem, the
DesignWare SoundWave Audio Subsystem. The product, rolled out in March, includes pre-verified hardware and software to reduce design and integration effort, decrease design risk and accelerate time-to-market, according to Synopsys. Koeter said
the subsystem includes configurable processing cores and interfaces and comes with more than 500,000 lines of software ported on top of it.
"I think this is really what the future of IP is," Koeter said.
Panelists from left: John Koeter of Synopsys, Kevin Meyer of Globalfoundries and Naveed Sherwani of Open-Silicon. Moderator Ron Wilson (right) is editor-in-chief at Altera.