EDA tools aims at 10-nanometer 3-D

EDA tools aims at 10-nanometer 3-D

PORTLAND, Ore.—Reaching the advanced semiconductor process nodes at 22-nanometer and beyond requires accurate three-dimensional (3-D) models of the proposed physical structures to obviate the need for repeated trial-and-error design cycles. In fact, the International Technology Roadmap for Semiconductors has designated modeling 3D physical structures as a "grand challenge" at advanced processing nodes.

One of the few tools capable of modeling the ultra-compact structures of FinFETs and other 3-D transistor structures is SEMulator3D, which was originally created by EDA software house Conventor Inc. (Cary, North Carolina) for MEMS designs, but which today is used almost exclusively for advanced semiconductor designs. IBM, for instance, has chosen SEMulator3D to design its FinFETs at the 22-nanometer node and beyond.

"SEMulator3D has helped IBM predict problems that otherwise would only have been found by subsequent testing and physical failure analysis," said David Fried, 22-nm chief technologist at IBM.

The latest iteration of SEMulator3D 2012 now supports 64-bit voxels (3-D pixels that can be filled with any semiconductor material) enabling ultra-accurate modeling of 3-D semiconductor structures at advanced processing nodes.


SEMulator3D can model the micro-electro-mechanical structures on the most advanced semiconductors such as this FinFET SRAM cells with a high-K metal gate.

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