LONDON – Applied Materials, the largest producer chipmaking equipment, and Singapore's Institute of Microelectronics have officially opened a center for advanced packaging at Science Park II in Singapore.
The center has been built with $100 million of investment from Applied Materials (Santa Clara, Calif.) and IME and features a 14,000 square foot Class-10 cleanroom and is equipped with a fully integrated manufacturing line for 300-mm wafers. The center is intended to support the R&D of 3-D wafer-level, chip packaging.
The use of through-silicon vias (TSVs) and the stacking of multiple die is expected to have a transformational effect on the semiconductor industry. When used to stack memory chips on logic chips, this technology is expected to reduce package size by 35 percent, decrease power consumption by 50 percent, and increase data bandwidth by a factor of eight or more times.
Research activities are already underway at the center with a team of over 50 personnel.
"Today, we are not only opening the most advanced wafer level packaging lab of its kind in the world, but we are also opening a new product development capability for Applied Materials in Asia," said Mike Splinter, chairman and CEO of Applied Materials, in a statement.
In the same statement Lim Chuan Poh, chairman of Singapore's Agency for Science, Technology and Research, said: "This will create many high-value jobs locally and help to further anchor Singapore's semiconductor manufacturing base."
"This collaboration will enable the semiconductor industry to accelerate the adoption of 3D chip packaging," said Professor Dim-Lee Kwong, executive director of IME, in the same statement.
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