SANTA CLARA, Calif. — The Gen-Z Consortium is showing prototypes of its memory-agnostic interconnect that aims to enable an emerging crop of persistent memories starting in 2019. It may see its first use in a high-performance DRAM modules in the works.
Executives from Hewlett-Packard Enterprise (HPE), Western Digital (WD), Lam Research and others said new memory types will disrupt memory and processor designs. Some pointed to Gen-Z as a key enabler in talks at the Flash Memory Summit here.
New kinds of phase-change, resistive and magneto-resistive memories have long sought to displace or complement flash and DRAM. To date they have carved out relatively small niches.
Some of the new memories “look as fast as DRAM, and continuous [process] improvement will make them even faster,” said Rick Gottscho, CTO of Lam Research, predicting today’s planar DRAM designs will eventually reach scaling limits.
One Holy Grail for the new memories is to become the center of a new class of processors, said Gottscho and others. As an example, he outlined a concept for a future machine-learning chip.
Neural network “weights could be stored not as digital quantities but as an analog resistance level…synapse-to-synapse, so you are not going off chip at all and have very rapid data transfer…The memory chip is the computer,” he said in a meeting with financial analysts at the event.
Western Digital discussed at least two approaches to memory-centric computing at the event. (Image: EE Times)
WD described a similar concept, showing a sea of low gate-count processors using an open instruction set surrounding a persistent memory. The company has announced it will deliver a ReRAM before 2020 and is supporting both the Gen-Z interconnect and the RISC-V ISA.
“The notion of proprietary interfaces off processors is nonsensical,” said Martin Fink, the chief technologist of WD, adding in a keynote that all the new memories will “have a role to play.”
“The transition to [the new memories] will follow same path as the current transition from hard drives to flash, initially in the cache tier,” said Siamak Nazari, chief software architect in the 3Par storage division of HPE. “Our first [new memory] products will seem pretty traditional, adding a new caching tier, but eventually storage and compute must be fused to get the full benefits,” he added.
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