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Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the first falling edge of TCK, TDO goes from the high-impedance state to an active state.SN74LVC161284DGGR Texas Instruments(TI) IC BUS INTERF TRI-STATE 48-TSSOP, TDO enables to the logic level present in the least-significant bit of the selected data register.While in the stable Shift-DR state, data is shifted serially through the selected data register on each TCK cycle.The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.SN74LVC161284DGGR Texas Instruments(TI) IC BUS INTERF TRI-STATE 48-TSSOP Improved Speed and Package Replacement for the SN75LBC976 Designed to Operate at up to 20 Million Data Transfers per Second (Fast-20 SCSI) Nine Differential Channels for the Data and Control Paths of the Small Computer Systems Interface (SCSI) and Intelligent Peripheral Interface (IPI) SN75976A Packaged in Shrink Small-Outline Package with 25-Mil Terminal Pitch (DL) and Thin Shrink Small-Outline Package with 20-Mil Terminal Pitch (DGG) SN55976A Packaged in a 56-Pin Ceramic Flat Pack (WD)Two Skew Limits Available ESD Protection on Bus Terminals Exceeds 12 kV Low Disabled Supply Current 8 mA Typ Thermal Shutdown Protection Positive- and Negative-Current LimitingPower-Up/Down Glitch Protection,SN74LVC161284DGGR Texas Instruments(TI) IC BUS INTERF TRI-STATE 48-TSSOP